The parallel transfer of the bits of data words between a processor and memory is along separate store and fetch paths. The store path proceeds from the controller of the memory to the central storage store buffers, to a set of dynamic random access memory chips (DRAMs) of the memory. The fetch path proceeds from the set of DRAMs to the central storage fetch buffers of the memory controller. The bit positions of the stored and fetched words are physically divided among different components that may have different latency characteristics (the time it takes to propagate data through the path). For example, a memory subsystem of a computer system can include multiple independent processor memory arrays (PMAs) that supply blocks of data in a plurality of parallel transfers of 64 bit wide data words. The bits of the data words come from different synchronous memory interface (SMI2) chips located on separate memory cards. The SMI2 chips communicate with the DRAMs of the memory subsystem and also with the main storage controller (MSC) chip. When the MSC chip receives a data word on the fetch data bus, it must capture all the 64 bits of a data word from the SMI2 chips within a capture window. Likewise, when the SMI2 chips receive data on the store data bus, they must also capture all 64 bits of a data word within a capture window. Both the SMI2 chips and the MSC chip have interface logic to capture data bits. However, there can be differences in the time it takes the bits in different bit positions of the data word to travel the paths between the SMI2 chips and the MSC chip because they travel through different paths with different latency characteristics. As a result, bits in the data words of the block can be misaligned with bits in one or more positions of one word arriving at their destination with bits in bit positions of other data words. The capture logic or windows are adjustable to accommodate different operating parameters in the chips. One method that is used to adjust these windows is a manual setting of the capture latches by trial and error. This method is time consuming and can require different adjustments of latches in different computers with the same model number.